1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having plural chips of different functions mounted in a single package, and a method of testing the same.
2. Description of Related Art
It has been proposed that a large scale system can be realized in a single package by adopting SiP (System in Package) structure in which plural chips having different functions, such as a memory chip and a logic chip are mounted on a single package. A semiconductor integrated circuit device using the SiP structure can only have limited number of input-output terminals arranged in the package. Therefore, in a common practice, it has no dedicated input-output terminals that allow direct external access to the memory chip, and the memory chip is accessed only through the input-output terminals for the logic chip so that the number of terminals is reduced.
FIG. 7 shows a block diagram of a semiconductor integrated circuit device 101 having MCP (Multi Chip Package) or MCM (Multi Chip Module) structure in accordance with related art 1 (Japanese Unexamined Patent Application Publication No. 2003-77296). In the semiconductor integrated circuit device 101 of the related art 1, a logic chip 2 and a memory chip 3 are mounted in a single package 1.
The logic chip 2 contains a logic circuit 2A, a memory chip test circuit 4, and a selector/input-output circuit 2C. The memory chip test circuit 4 is provided to carry out an operation test for the memory chip 3. The selector/input-output circuit 2C is provided to carry out switching between access signals from the logic circuit 2A and access signals from the memory chip test circuit 4 for the test.
The device is configured such that the memory chip 3 is accessed through the logic chip 2. That is, the memory chip 3 is not directly connected to any external terminals of the package 1, and configured such that data is inputted to or outputted from the memory chip 3 in response to an access request from the logic chip 2. A clock terminal 22, control signal terminals 23, address terminals 24, and data terminals 25 of the logic chip 2 are connected to corresponding terminals 32, 33, 34, and 35 respectively of the memory chip. Plural input-output terminals 20 of the logic chip are connected to external terminals 10 of the package 1.
The access operation from the logic chip 2 to the memory chip 3 is carried out in the following manner. That is, during the normal operation, the memory access signals are supplied from the logic circuit 2A to the memory chip 3 through the selector/input-output circuit 2C. On the other hand, during the memory chip test, the access signals for the memory chip test are supplied from the memory chip test circuit 4 provided in the logic chip 2 to the memory chip 3 through the selector/input-output circuit 2C. With the above-described structure, a high speed operation test can be carried out even after the burn-in that is carried out after the chips are mounted in the package.
FIG. 8 shows a block diagram of semiconductor integrated circuit device 102 having a test interface circuit 2 in accordance with related art 2 (Japanese Unexamined Patent Application Publication No. 2004-55030) Similarly to the above-mentioned related art 1, a logic chip and a memory chip (internal memory) 3 are mounted in a single package in the semiconductor integrated circuit device 102. The logic chip contains the test interface circuit 2. A memory transfer circuit 4, which transfers data to an internal memory 3 that is mounted in the same package, is provided in the test interface circuit 2. A plurality of input-output terminals are provided in the semiconductor integrated circuit device 102. For example, terminals for a signal that determines signal transfer timing to the internal memory 3 (TCLK), a signal that determines signal/data fetch timing of the internal memory (CLK), a latch timing signal to sample a signal read out from the internal memory (MLAT), and a test clock signal for compensation (TCLKcal) are provided.
In the semiconductor integrated circuit device 102 in accordance with the related art 2, the above-mentioned various signals, i.e., TCLK, CLK, and MLAT are sampled in accordance with the above-mentioned TCLKcal by the common flip-flop circuit 6 provided in the test interface circuit 2 in order to accurately measure timing conditions such as a set-up time and a hold time. Furthermore, it discloses a structure in which phase differences of these latch timing signal, test clock signal, and memory clock signal are externally measured.
Japanese Unexamined Patent Application Publication No. 2003-43117 has proposed a structure in which a set-up time and a hold time are controlled by a delay circuit arranged in the device so that they satisfy their specified values.
In the semiconductor integrated circuit device 101 in accordance with the related art 1, since the test circuit 4 for the memory chip test is arranged in the logic chip 2, a pattern that is used to carry out the operation test of the memory chip cannot be simple. However, if a complicated pattern is incorporated, the test circuit becomes larger in scale.
In the semiconductor integrated circuit device 102 in accordance with the related art 2, since a plurality of external terminals are used to adjust the operation timing of the internal circuit, the total number of pins is increased. If the number of pins becomes larger, it leads to a larger package size. In the semiconductor integrated circuit device in accordance with the above-mentioned Japanese Unexamined Patent Application Publication No. 2003-43117, it raises problems like one that since the circuit includes the delay circuit, the circuit structure becomes more complicated and the circuit becomes larger in scale. Furthermore, since it involves variations in the delay circuit itself, accurate testing is difficult to carry out.